1 sep-02-2004 n-channel logic level enhancement mode field eff ect transistor P45N02LDG to-252 (dpak) lead-free niko-sem absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol limits units gate-source voltage v gs 20 v t c = 25 c 45 continuous drain current t c = 100 c i d 28 pulsed drain current 1 i dm 140 avalanche current i ar 20 a avalanche energy l = 0.1mh e as 140 repetitive avalanche energy 2 l = 0.05mh e ar 5.6 mj t c = 25 c 55 power dissipation t c = 100 c p d 33 w operating junction & storage temperature range t j , t stg -55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-case r jc 3 junction-to-ambient r ja 70 case-to-heatsink r cs 0.7 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1 h electrical characteristics (t c = 25 c, unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain-source breakdown voltage v (br)dss v gs = 0v, i d = 250 a 25 gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.8 1.2 2.5 v gate-body leakage i gss v ds = 0v, v gs = 20v 250 na v ds = 20v, v gs = 0v 25 zero gate voltage drain current i dss v ds = 20v, v gs = 0v, t j = 125 c 250 a on-state drain current 1 i d(on) v ds = 10v, v gs = 10v 45 a 1. gate 2. drain 3. source product summary v (br)dss r ds(on) i d 25 20m [ 45a g d s free datasheet http://www.datasheet-pdf.com/
2 sep-02-2004 n-channel logic level enhancement mode field eff ect transistor P45N02LDG to-252 (dpak) lead-free niko-sem v gs = 7v, i d = 18a 20 30 drain-source on-state resistance 1 r ds(on) v gs = 10v, i d = 20a 15 28 m [ forward transconductance 1 g fs v ds = 15v, i d = 30a 16 s dynamic input capacitance c iss 600 output capacitance c oss 290 reverse transfer capacitance c rss v gs = 0v, v ds = 15v, f = 1mhz 100 pf total gate charge 2 q g 25 gate-source charge 2 q gs 2.9 gate-drain charge 2 q gd v ds = 0.5v (br)dss , v gs = 10v, i d = 20a 7.0 nc turn-on delay time 2 t d(on) 7.0 rise time 2 t r v ds = 15v, r l = 1 [ 7.0 turn-off delay time 2 t d(off) i d ? 30a, v gs = 10v, r gs = 2.5 [ 24 fall time 2 t f 6.0 ns source-drain diode ratings and characteristics (t c = 25 c) continuous current i s 45 pulsed current 3 i sm 150 a forward voltage 1 v sd i f = i s , v gs = 0v 1.3 v reverse recovery time t rr 37 ns peak reverse recovery current i rm(rec) i f = i s , dl f /dt = 100a / s 200 a reverse recovery charge q rr 0.043 c 1 pulse test : pulse width 300 sec, duty cycle 2 h . 2 independent of operating temperature. 3 pulse width limited by maximum junction temperature. remark: the product marked with ?p 45n02ldg?, date code or lot # orders for parts with lead-free plating can be placed using the pxxxxxxg parts name free datasheet http://www.datasheet-pdf.com/
3 sep-02-2004 n-channel logic level enhancement mode field eff ect transistor P45N02LDG to-252 (dpak) lead-free niko-sem typical characteristics free datasheet http://www.datasheet-pdf.com/
4 sep-02-2004 n-channel logic level enhancement mode field eff ect transistor P45N02LDG to-252 (dpak) lead-free niko-sem free datasheet http://www.datasheet-pdf.com/
5 sep-02-2004 n-channel logic level enhancement mode field eff ect transistor P45N02LDG to-252 (dpak) lead-free niko-sem to-252 (dpak) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 9.35 10.4 h 0.89 2.03 b 2.2 2.4 i 6.35 6.80 c 0.45 0.6 j 5.2 5.5 d 0.89 1.5 k 0.6 1 e 0.45 0.69 l 0.5 0.9 f 0.03 0.23 m 3.96 4.57 5.18 g 5.2 6.2 n g a h j i b c m l k d e f 13 2 free datasheet http://www.datasheet-pdf.com/
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